On Mon, Dec 08, 2014 at 09:01:39AM -0600, Segher Boessenkool wrote:
> > Why are you removing the alternative instead of clobbering XER[CA]?
>
> I should have mentioned, sorry.
>
> We don't want to clobber CA on *every* add, and reload can generate more
> adds out of thin air. And CA is a fixed r
On Tue, Dec 09, 2014 at 11:48:44AM -0500, David Edelsohn wrote:
> We definitely will have to define addptrM3 and restore addM3 when
> rs6000 switches to LRA.
Can LRA deal with adding a clobber of a hard register? How would
you express that in the patterns, anyway?
Segher
On Tue, Dec 9, 2014 at 11:24 AM, Eric Botcazou wrote:
>> It's unfortunate that GCC does not have separate patterns for a safe
>> ADD used by reload.
>
> It does, the addptrM3 pattern, but it works only with LRA at the moment.
Hi, Eric
Segher and I previously discussed addptrM3, but I thought tha
> It's unfortunate that GCC does not have separate patterns for a safe
> ADD used by reload.
It does, the addptrM3 pattern, but it works only with LRA at the moment.
--
Eric Botcazou
On Mon, Dec 8, 2014 at 10:01 AM, Segher Boessenkool
wrote:
> On Mon, Dec 08, 2014 at 09:44:44AM -0500, David Edelsohn wrote:
>> > -;; Discourage ai/addic because of carry but provide it in an alternative
>> > -;; allowing register zero as source.
>> > (define_insn "*add3_internal1"
>> > - [(set
On Mon, Dec 08, 2014 at 09:44:44AM -0500, David Edelsohn wrote:
> > -;; Discourage ai/addic because of carry but provide it in an alternative
> > -;; allowing register zero as source.
> > (define_insn "*add3_internal1"
> > - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
> > - (p
On Mon, Dec 8, 2014 at 9:18 AM, Segher Boessenkool
wrote:
> This means we can no longer add GPR0+imm. Register allocation will have
> to use a different register.
>
>
> 2014-12-08 Segher Boessenkool
>
> gcc/
> PR target/64180
> * config/rs6000/rs6000.md (*add3_internal1): Remov
