Re: [PATCH] minimal support for xtheadv

Give a few more thought behind my first LGTM: I am OK *IF* binutils bits accepted since it's just kind of bypassing the -march to bintuils to enable those instructions for assembly code. However the situation seems is little more complicated than my expect at beginning...:P Anyway, I still think

Re: [PATCH] minimal support for xtheadv

On 11/9/23 01:38, Yixuan Chen wrote: Hi Kito and Christoph, XYenChi (oriachi...@gmail.com ) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so po

Re: [PATCH] minimal support for xtheadv

Hi Kito and Christoph, XYenChi (oriachi...@gmail.com) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so port the XTheadV. If T-Head and VRULL have made great progress, it's pleasure

Re: [PATCH] minimal support for xtheadv

On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng wrote: > > Hi Yi Xuan: > > This patch is trivial, and generally LGTM, but I would require putting > the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions > before merging this, also don't forget include "RISC-V:" in the title, > it wou

Re: [PATCH] minimal support for xtheadv

Hi Yi Xuan: This patch is trivial, and generally LGTM, but I would require putting the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions before merging this, also don't forget include "RISC-V:" in the title, it would be easier to track during the RISC-V GCC sync meeting :) An