On 4/10/25 5:29 PM, Jakub Jelinek wrote:
On Thu, Apr 10, 2025 at 05:13:12PM +0530, Tejas Belagod wrote:
Thanks for the explanation. I looked into why some of the tests may have
failed - my flawed understanding of the reduction clause was why I didn't
have the += in the loops - it might have pas
Tejas Belagod writes:
> On 4/10/25 5:56 PM, Richard Sandiford wrote:
>> Tejas Belagod writes:
>>> Sorry, forgot to ask - Richard, are you happy for me to work on a
>>> separate patch to fix the test alongside your target +sve fix as a
>>> couple more functions (eg simd_reduction () and inscan.. (
On 4/9/25 4:13 PM, Jakub Jelinek wrote:
On Wed, Apr 09, 2025 at 04:01:49PM +0530, Tejas Belagod wrote:
It also looks like there might be a missing "+" in simd_reduction:
#pragma omp simd reduction (+:va, i)
for (j = 0; j < 16; j++)
va = svld1_s32 (svptrue_b32 (), a);
res = sv
On 4/10/25 5:56 PM, Richard Sandiford wrote:
Tejas Belagod writes:
On 4/10/25 5:13 PM, Tejas Belagod wrote:
On 4/9/25 4:13 PM, Jakub Jelinek wrote:
On Wed, Apr 09, 2025 at 04:01:49PM +0530, Tejas Belagod wrote:
It also looks like there might be a missing "+" in simd_reduction:
#pragma
On Thu, Apr 10, 2025 at 05:13:12PM +0530, Tejas Belagod wrote:
> Thanks for the explanation. I looked into why some of the tests may have
> failed - my flawed understanding of the reduction clause was why I didn't
> have the += in the loops - it might have passed for me as I probably hit the
> exa
Tejas Belagod writes:
> On 4/10/25 5:13 PM, Tejas Belagod wrote:
>> On 4/9/25 4:13 PM, Jakub Jelinek wrote:
>>> On Wed, Apr 09, 2025 at 04:01:49PM +0530, Tejas Belagod wrote:
> It also looks like there might be a missing "+" in simd_reduction:
>
> #pragma omp simd reduction (+:va,
On 4/10/25 5:13 PM, Tejas Belagod wrote:
On 4/9/25 4:13 PM, Jakub Jelinek wrote:
On Wed, Apr 09, 2025 at 04:01:49PM +0530, Tejas Belagod wrote:
It also looks like there might be a missing "+" in simd_reduction:
#pragma omp simd reduction (+:va, i)
for (j = 0; j < 16; j++)
va = sv
On Wed, Apr 09, 2025 at 04:01:49PM +0530, Tejas Belagod wrote:
> > It also looks like there might be a missing "+" in simd_reduction:
> >
> >#pragma omp simd reduction (+:va, i)
> >for (j = 0; j < 16; j++)
> > va = svld1_s32 (svptrue_b32 (), a);
> >
> >res = svaddv_s32 (svptrue_b
On 4/9/25 2:32 AM, Richard Sandiford wrote:
The new SVE tests didn't explicitly force SVE to be enabled,
which meant that they wouldn't work on targets that aren't
configured for SVE by default. The least invasive way of
fixing that is to add a pragma, which works for most tests.
However, for ud
