RE: [PATCH] libatomic: Improve ifunc selection on AArch64

> -Original Message- > From: Wilco Dijkstra > Sent: Friday, November 10, 2023 10:23 AM > To: Kyrylo Tkachov ; GCC Patches patc...@gcc.gnu.org>; Richard Sandiford > Subject: Re: [PATCH] libatomic: Improve ifunc selection on AArch64 > > Hi Kyrill, > >

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

Hi Kyrill, > +  if (!(hwcap & HWCAP_CPUID)) > +    return false; > + > +  unsigned long midr; > +  asm volatile ("mrs %0, midr_el1" : "=r" (midr)); > From what I recall that midr_el1 register is emulated by the kernel and so > userspace software > has to check that the kernel supports that emula

RE: [PATCH] libatomic: Improve ifunc selection on AArch64

Hi Wilco, > -Original Message- > From: Wilco Dijkstra > Sent: Monday, November 6, 2023 12:13 PM > To: GCC Patches ; Richard Sandiford > > Cc: Kyrylo Tkachov > Subject: Re: [PATCH] libatomic: Improve ifunc selection on AArch64 > > > > ping >

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

  ping From: Wilco Dijkstra Sent: 04 August 2023 16:05 To: GCC Patches ; Richard Sandiford Cc: Kyrylo Tkachov Subject: [PATCH] libatomic: Improve ifunc selection on AArch64   Add support for ifunc selection based on CPUID register.  Neoverse N1 supports atomic 128-bit load/store, so use the

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

  ping From: Wilco Dijkstra Sent: 04 August 2023 16:05 To: GCC Patches ; Richard Sandiford Cc: Kyrylo Tkachov Subject: [PATCH] libatomic: Improve ifunc selection on AArch64   Add support for ifunc selection based on CPUID register.  Neoverse N1 supports atomic 128-bit load/store, so use the

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

ping From: Wilco Dijkstra Sent: 04 August 2023 16:05 To: GCC Patches ; Richard Sandiford Cc: Kyrylo Tkachov Subject: [PATCH] libatomic: Improve ifunc selection on AArch64   Add support for ifunc selection based on CPUID register.  Neoverse N1 supports atomic 128-bit load/store, so use the F

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

Hi Richard, >>> Answering my own question, N1 does not officially have FEAT_LSE2. >> >> It doesn't indeed. However most cores support atomic 128-bit load/store >> (part of LSE2), so we can still use the LSE2 ifunc for those cores. Since >> there >> isn't a feature bit for this in the CPU or HWCA

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

On 8/10/23 02:50, Wilco Dijkstra wrote: Hi Richard, Why would HWCAP_USCAT not be set by the kernel? Failing that, I would think you would check ID_AA64MMFR2_EL1.AT. Answering my own question, N1 does not officially have FEAT_LSE2. It doesn't indeed. However most cores support atomic 128-bi

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

Hi Richard, >> Why would HWCAP_USCAT not be set by the kernel? >> >> Failing that, I would think you would check ID_AA64MMFR2_EL1.AT. >> > Answering my own question, N1 does not officially have FEAT_LSE2. It doesn't indeed. However most cores support atomic 128-bit load/store (part of LSE2), so

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

On 8/9/23 19:11, Richard Henderson wrote: On 8/4/23 08:05, Wilco Dijkstra via Gcc-patches wrote: +#ifdef HWCAP_USCAT + +#define MIDR_IMPLEMENTOR(midr)    (((midr) >> 24) & 255) +#define MIDR_PARTNUM(midr)    (((midr) >> 4) & 0xfff) + +static inline bool +ifunc1 (unsigned long hwcap) +{ +  if (hw

Re: [PATCH] libatomic: Improve ifunc selection on AArch64

On 8/4/23 08:05, Wilco Dijkstra via Gcc-patches wrote: +#ifdef HWCAP_USCAT + +#define MIDR_IMPLEMENTOR(midr) (((midr) >> 24) & 255) +#define MIDR_PARTNUM(midr) (((midr) >> 4) & 0xfff) + +static inline bool +ifunc1 (unsigned long hwcap) +{ + if (hwcap & HWCAP_USCAT) +return true; + if (!