Dhruv Chawla writes:
> This patch modifies Advanced SIMD assembly generation to emit an LDR
> instruction when a vector is created using a load to the first element with
> the
> other elements being zero.
>
> This is similar to what *aarch64_combinez already does.
>
> Example:
>
> uint8x16_t foo(
On 06/01/25 11:44, Andrew Pinski wrote:
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On Sun, Jan 5, 2025 at 10:06 PM Dhruv Chawla wrote:
This patch modifies Advanced SIMD assembly generation to emit an LDR
instruction when a vector is created using a load to the first element wit
On Sun, Jan 5, 2025 at 10:06 PM Dhruv Chawla wrote:
>
> This patch modifies Advanced SIMD assembly generation to emit an LDR
> instruction when a vector is created using a load to the first element with
> the
> other elements being zero.
>
> This is similar to what *aarch64_combinez already does.
