> I will also fix all the other points you raised.
> Thanks!
You're welcome. And if you want to have commit rights to the SVN
repository,
you can put me as your sponsor (Eric Botcazou ).
I just sent a request. Thank you.
> I think I will change v3pipe to v3pipe_m7 in this patch, to make it more
> explicit that the insn<->v3pipe association is processor-dependant.
No strong opinion, IOW it's your call.
> Yes, it is intended. I will add a little note.
Thanks.
> I will also fix all the other points you raised.
>
Hi Eric.
> The niagara7 pipeline description models the V3 pipe using a bypass
> with latency 3, from-to any instruction executing in the V3 pipe. The
> instructions are identified by mean of a new instruction attribute
> "v3pipe", that has been added to the proper define
> This patch adds support for -mcpu=niagara7, corresponding to the SPARC
> M7 CPU as documented in the Oracle SPARC Architecture 2015 and the M7
> Processor Supplement. The patch also includes intrinsics support for
> all the VIS 4.0 instructions.
Thanks for contributing this.
> This patch has b
