Re: [PATCH] RISC-V: Make zero-stride load broadcast a tunable.

Oh, I guess I didn't expand enough about my thought: I don't care that we have bad performance/bad code gen here if Zvfh is mandatory for RVA23 since that means not many people and core will fall into this code gen path. But RVA23 will go to this code gen patch, which means we will go this path fo

Re: [PATCH] RISC-V: Make zero-stride load broadcast a tunable.

On Thu, Jul 10, 2025 at 5:31 PM Robin Dapp wrote: > > >> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > >> index 6753b01db59..866aaf1e8a0 100644 > >> --- a/gcc/config/riscv/vector.md > >> +++ b/gcc/config/riscv/vector.md > >> @@ -1580,8 +1580,27 @@ (define_insn_and_split "*

Re: [PATCH] RISC-V: Make zero-stride load broadcast a tunable.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6753b01db59..866aaf1e8a0 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1580,8 +1580,27 @@ (define_insn_and_split "*vec_duplicate" "&& 1" [(const_int 0)] { -riscv_vector::emit_vlma

Re: [PATCH] RISC-V: Make zero-stride load broadcast a tunable.

> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 6753b01db59..866aaf1e8a0 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1580,8 +1580,27 @@ (define_insn_and_split "*vec_duplicate" >"&& 1" >[(const_int 0)] >{ > -riscv_