On 5/23/24 11:52 PM, Richard Biener wrote:
This worked out so I pushed the change. The gcc.dg/vect/pr97428.c
test is FAILing on RISC-V (it still gets 0 SLP), because of missed
load permutations. I hope the followup reorg for the load side will
fix this. It also FAILs gcc.target/riscv/rvv/
On Thu, 23 May 2024, Richard Biener wrote:
> The following avoids splitting store dataref groups during SLP
> discovery but instead forces (eventually single-lane) consecutive
> lane SLP discovery for all lanes of the group, creating VEC_PERM
> SLP nodes merging them so the store will always cover
