On Thu, 04 May 2017 05:40:35 PDT (-0700), Palmer Dabbelt wrote:
> From: Andrew Waterman
>
> The RISC-V user ISA permits misaligned accesses, but they may trap
> and be emulated. That emulation software needs to be compiled assuming
> strict alignment.
>
> Even when strict alignment is not require
On Mon, 01 May 2017 10:08:08 PDT (-0700), san...@codesourcery.com wrote:
> On 05/01/2017 09:40 AM, Palmer Dabbelt wrote:
>> [snip]
>>
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index 0466bb2..0422e07 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/risc
On 05/01/2017 09:40 AM, Palmer Dabbelt wrote:
[snip]
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0466bb2..0422e07 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -84,6 +84,10 @@ mcmodel=
Target Report RejectNegative Joined Enum(code_mo