as.ac.cn, oriachi...@gmail.com, shi...@iscas.ac.cn,
jia...@iscas.ac.cn
> Subject: Re: [PATCH] Add VXRM enum
>
> Those enum values have been defined via `#pragma riscv intrinsic "vector"`
:)
>
>
https://github.com/gcc-mirror/gcc/commit/01d62e9b6c3e9fd3132f1616843103ccf81778ed
>
Those enum values have been defined via `#pragma riscv intrinsic "vector"` :)
https://github.com/gcc-mirror/gcc/commit/01d62e9b6c3e9fd3132f1616843103ccf81778ed
On Thu, Jul 13, 2023 at 2:55 PM Robin Dapp via Gcc-patches
wrote:
>
> > +enum __RISCV_VXRM {
> > + __RISCV_VXRM_RNU = 0,
> > + __RISCV
> +enum __RISCV_VXRM {
> + __RISCV_VXRM_RNU = 0,
> + __RISCV_VXRM_RNE = 1,
> + __RISCV_VXRM_RDN = 2,
> + __RISCV_VXRM_ROD = 3,
> +};
> +
> __extension__ extern __inline unsigned long
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vread_csr(enum RVV_CSR csr)
We have
