> On 29 Apr 2025, at 18:21, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
>> ptrue predicate can be replaced by neon instructions (LDR and STR),
>> th
Jennifer Schmitz writes:
> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
> ptrue predicate can be replaced by neon instructions (LDR and STR),
> thus avoiding the predicate altogether. This also enables formation of
> LDP/STP pairs.
>
> For example, the test cases
>
> svfloat
> On 29 Apr 2025, at 14:03, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
>> index f7bccf532f8..1c06b8528e9 100644
>> --- a/gcc/config/aarch64/
Jennifer Schmitz writes:
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index f7bccf532f8..1c06b8528e9 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -6416,13 +6416,30 @@ aarch64_stack_protect_canary_mem (machine_mode mode,
> On 28 Apr 2025, at 15:35, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>>> On 25 Apr 2025, at 19:55, Richard Sandiford
>>> wrote:
>>>
>>> Jennifer Schmitz writes:
If -msve-vector-bits=128, SVE loads and stores (
Kyrylo Tkachov writes:
>> On 25 Apr 2025, at 19:55, Richard Sandiford
>> wrote:
>>
>> Jennifer Schmitz writes:
>>> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
>>> ptrue predicate can be replaced by neon instructions (LDR and STR),
>>> thus avoiding the predicate altoget
> On 25 Apr 2025, at 19:55, Richard Sandiford wrote:
>
> Jennifer Schmitz writes:
>> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
>> ptrue predicate can be replaced by neon instructions (LDR and STR),
>> thus avoiding the predicate altogether. This also enables formation
>>> To: Jennifer Schmitz
>>> Cc: gcc-patches@gcc.gnu.org
>>> Subject: Re: [PATCH] AArch64: Fold LD1/ST1 with ptrue to LDR/STR for
>>> 128-bit VLS
>>>
>>> Jennifer Schmitz writes:
>>>> If -msve-vector-bits=128, SVE loads and
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Friday, April 25, 2025 6:55 PM
>> To: Jennifer Schmitz
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH] AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit
&g
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, April 25, 2025 6:55 PM
> To: Jennifer Schmitz
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit
> VLS
>
> Jennifer Schmitz writes:
&
Jennifer Schmitz writes:
> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
> ptrue predicate can be replaced by neon instructions (LDR and STR),
> thus avoiding the predicate altogether. This also enables formation of
> LDP/STP pairs.
>
> For example, the test cases
>
> svfloat
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