> -Original Message-
> From: Jakub Jelinek
> Sent: Friday, February 7, 2025 4:08 PM
> To: Liu, Hongtao
> Cc: gcc-patches@gcc.gnu.org
> Subject: [PATCH] i386: Fix ICE with conditional QI/HI vector maxmin
> [PR118776]
>
> Hi!
>
> The following testcase ICEs starting with GCC 12 since r
On Wed, Dec 13, 2023 at 4:44 PM Jakub Jelinek wrote:
>
> Hi!
>
> The following patch fixes ICE on the testcase in similar way to how
> other folded builtins are handled in ix86_gimple_fold_builtin when
> they don't have a lhs; these builtins are const or pure, so normally
> DCE would remove them l
On Fri, Nov 24, 2023 at 9:31 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because cbranchv16qi4 expansion calls
> ix86_expand_branch with op1 being a pre-AVX unaligned memory and
> ix86_expand_branch emits a xorv16qi3 instruction without making sure
> the operand predicates are
On Fri, May 13, 2022 at 1:43 PM liuhongt wrote:
>
> When d->perm[i] == d->perm[i-1] + 1 and d->perm[i] == nelt, it's not
> continuous. It should fail if there's more than 2 continuous areas.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
>
> gcc/ChangeLog:
>
>
On Mon, Apr 11, 2022 at 6:50 PM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because ix86_emit_i387_log1p attempts to
> emit something like
> if (cond)
> some_code1;
> else
> some_code2;
> and emits a conditional jump using emit_jump_insn (standard way in
> the file) a
Here's the patch I'm going to check in, the patch is pre-approved in PR.
On Thu, Jan 13, 2022 at 11:59 PM liuhongt wrote:
>
> For define_insn_and_split "*xor2andn":
>
> 1. Refine predicate of operands[0] from nonimmediate_operand to
> register_operand.
> 2. Remove TARGET_AVX512BW from condition t
On Tue, Nov 30, 2021 at 10:43 AM liuhongt wrote:
>
> ix86_attr_length_immediate_default assume TYPE ishift only have 1
> constant operand,
> but *x86_64_shld_1/*x86_shld_1/*x86_64_shrd_1/*x86_shrd_1 has 2, with
> condition: INTVAL (operands[3]) == 32 - INTVAL (operands[2]) or
> INTVAL (operands[3]
On Tue, Nov 30, 2021 at 5:44 PM liuhongt via Gcc-patches
wrote:
>
> ix86_attr_length_immediate_default assume TYPE ishift only have 1
> constant operand,
> but *x86_64_shld_1/*x86_shld_1/*x86_64_shrd_1/*x86_shrd_1 has 2, with
> condition: INTVAL (operands[3]) == 32 - INTVAL (operands[2]) or
> INTV
On Sat, Sep 18, 2021 at 03:56:42PM +0800, Hongtao Liu wrote:
> > Wouldn't it be better to do:
> > E_VOIDmode:
> > gcc_assert (convert_p);
> !convert_p, Must be typo :)
Yes, sorry.
>
> > break;
> > default:
> > gcc_unreachable ();
> > ?
> Sur
On Sat, Sep 18, 2021 at 3:31 PM Jakub Jelinek wrote:
>
> On Sat, Sep 18, 2021 at 11:09:32AM +0800, liuhongt wrote:
> > Besides conversion instructions, pass_rpad also handles scalar
> > sqrt/rsqrt/rcp/round instructions, while r12-3614 should only want to
> > handle conversion instructions, so fix
On Sat, Sep 18, 2021 at 11:09:32AM +0800, liuhongt wrote:
> Besides conversion instructions, pass_rpad also handles scalar
> sqrt/rsqrt/rcp/round instructions, while r12-3614 should only want to
> handle conversion instructions, so fix it.
>
> Bootstrapped and regtest on x86_64-linux-gnu{-m32,}
On Mon, Aug 16, 2021 at 11:19 AM liuhongt wrote:
>
> Hi:
> avx512f_scalef2 only accept register_operand for operands[1],
> force it to reg in ldexp3.
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> Ok for trunk.
>
> gcc/ChangeLog:
>
> PR target/101930
> * config/
On Fri, Jun 04, 2021 at 01:03:58AM +, Liu, Hongtao wrote:
> Thanks for the review.
> Yes, you're right, AVX512VL parts are already guaranteed by
> ix86_hard_regno_mode_ok.
>
> Here is updated patch.
One remaining thing, could you try to modify the testcase back to
#include and using intrins
>-Original Message-
>From: Jakub Jelinek
>Sent: Thursday, June 3, 2021 9:49 PM
>To: Liu, Hongtao
>Cc: gcc-patches@gcc.gnu.org
>Subject: Re: [PATCH] [i386] Fix ICE of insn does not satisfy its constraints.
>
>On Thu, Jun 03, 2021 at 05:07:26PM +0800, liuhon
On Thu, Jun 03, 2021 at 05:07:26PM +0800, liuhongt via Gcc-patches wrote:
> @@ -18163,10 +18163,10 @@ (define_expand "v16qiv16si2"
>"TARGET_AVX512F")
>
> (define_insn "avx2_v8qiv8si2"
> - [(set (match_operand:V8SI 0 "register_operand" "=v")
> + [(set (match_operand:V8SI 0 "register_operand
On Tue, Sep 6, 2016 at 5:06 PM, Jakub Jelinek wrote:
> On Mon, Sep 05, 2016 at 08:58:12PM +0200, Uros Bizjak wrote:
>> ... perhaps we can emit a warning here and expand the builtin as a
>> call? This way, we will mirror the case when builtin requires some
>> ISA, e.g.:
>>
>> void foo ()
>> {
>>
On Mon, Sep 05, 2016 at 08:58:12PM +0200, Uros Bizjak wrote:
> ... perhaps we can emit a warning here and expand the builtin as a
> call? This way, we will mirror the case when builtin requires some
> ISA, e.g.:
>
> void foo ()
> {
> __builtin_ia32_stmxcsr();
> }
>
> $ gcc -S -mno-sse dd.c
> dd
On Mon, Sep 5, 2016 at 7:14 PM, Jakub Jelinek wrote:
> Hi!
>
> As the testcase shows, if we want to diagnose a md builtin not enabled in
> the current ISA, we call error and then return const0_rtx. That isn't a
> good choice if the result is BLKmode, which can happen for vector modes
> that aren'
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