Hi Mike,
Thanks for your comments.
Please find my comments inlined.
- Thanks and regards,
Sameera D.
On Monday 11 May 2015 10:09 PM, Mike Stump wrote:
On May 11, 2015, at 4:05 AM, sameera wrote:
+(define_insn "*join2_loadhi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (an
On May 11, 2015, at 4:05 AM, sameera wrote:
>>> +(define_insn "*join2_loadhi"
>>> + [(set (match_operand:SI 0 "register_operand" "=r")
>>> + (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m")))
>>> + (set (match_operand:SI 2 "register_operand" "=r")
>>> + (any_extend:SI (mat
On Monday 11 May 2015 05:43 PM, Matthew Fortune wrote:
Hi Sameera,
Sameera Deshpande writes:
Changelog:
gcc/
* config/mips/mips.md (JOIN_MODE): New mode iterator.
(join2_load_Store): New pattern.
(join2_loadhi): Likewise.
(define_peehole2): Add peephole2
Hi Sameera,
Sameera Deshpande writes:
> Changelog:
> gcc/
> * config/mips/mips.md (JOIN_MODE): New mode iterator.
> (join2_load_Store): New pattern.
> (join2_loadhi): Likewise.
> (define_peehole2): Add peephole2 patterns to join 2
> HI/SI/SF/DF-mode
>
On Tuesday 21 April 2015 12:39 AM, Matthew Fortune wrote:
Sameera Deshpande writes:
Gentle reminder!
Thanks Sameera. Just a couple of comments inline below and a question
for Catherine at the end.
- Thanks and regards,
Sameera D.
On Monday 30 March 2015 04:58 PM, sameera wrote:
Hi!
S
> -Original Message-
> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> Sent: Monday, April 20, 2015 3:10 PM
> To: Sameera Deshpande; Moore, Catherine
> Cc: Richard Sandiford; gcc-patches@gcc.gnu.org; echri...@gmail.com
> Subject: RE: [PATCH][MIPS] Enable loa
Sameera Deshpande writes:
> Gentle reminder!
Thanks Sameera. Just a couple of comments inline below and a question
for Catherine at the end.
> - Thanks and regards,
>Sameera D.
>
> On Monday 30 March 2015 04:58 PM, sameera wrote:
> > Hi!
> >
> > Sorry for delay in sending this patch for rev
With FUSION you might get farther. See the arm port as I recall.
The quick overview, FUSION allows instructions that are not contiguous to be
paired up and fused together. it was built for load/load store/store combining.
On Apr 19, 2015, at 10:09 PM, sameera wrote:
> Gentle reminder!
>
> -
Gentle reminder!
- Thanks and regards,
Sameera D.
On Monday 30 March 2015 04:58 PM, sameera wrote:
Hi!
Sorry for delay in sending this patch for review.
Please find attached updated patch.
In P5600, 2 consecutive loads/stores of same type which access contiguous
memory locations are bonded
Hi!
Sorry for delay in sending this patch for review.
Please find attached updated patch.
In P5600, 2 consecutive loads/stores of same type which access contiguous memory locations are bonded together by instruction issue unit to dispatch
single load/store instruction which accesses both locati
Hi Richard,
Thanks for the review.
Please find attached updated patch after your review comments.
Changelog:
gcc/
* config/mips/mips.md (JOIN_MODE): New mode iterator.
(join2_load_Store): New pattern.
(join2_loadhi): Likewise.
(define_peehole2): Add peephole2 patte
Sameera Deshpande writes:
>> > + if (TARGET_FIX_24K && TUNE_P5600)
>> > +error ("unsupported combination: %s", "-mtune=p5600 -mfix-24k");
>> > +
>> >/* Save the base compression state and process flags as though we
>> > were generating uncompressed code. */
>> >mips_base_compre
Hi Richard,
Thanks for your comments. I am working on the review comments, and will share
the reworked patch soon.
However, here is clarification on some of the issues raised.
> > + if (TARGET_FIX_24K && TUNE_P5600)
> > +error ("unsupported combination: %s", "-mtune=p5600 -mfix-24k");
> > +
Hi Sameera,
Thanks for the patch.
Sameera Deshpande writes:
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index b5b5ba7..9804ef2 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -18813,6 +18813,9 @@ mips_option_override (void)
>if (TARGET_MICROMIPS
14 matches
Mail list logo
