o Menezes
> Cc: gcc-patches; James Greenhalgh; Marcus Shawcroft; Philipp Tomsich
> Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP &
> STP
>
> On Tue, Sep 29, 2015 at 12:52 AM, Evandro Menezes
> wrote:
> > In some micro-architectures the in
On Tue, Sep 29, 2015 at 12:52 AM, Evandro Menezes wrote:
> In some micro-architectures the insns to load or store pairs of vector
> registers are implemented rather differently from those affecting lanes in
> vector registers. Then, it's important that such insns be described
> likewise different
; Evandro Menezes; gcc-patches@gcc.gnu.org
> Cc: James Greenhalgh; Ramana Radhakrishnan
> Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP &
> STP
>
>
> On 29/09/15 09:03, Marcus Shawcroft wrote:
> > On 29/09/15 00:52, Evandro Menezes wrote:
On 29/09/15 09:03, Marcus Shawcroft wrote:
On 29/09/15 00:52, Evandro Menezes wrote:
In some micro-architectures the insns to load or store pairs of vector
registers are implemented rather differently from those affecting lanes
in vector registers. Then, it's important that such insns be descr
On 29/09/15 00:52, Evandro Menezes wrote:
In some micro-architectures the insns to load or store pairs of vector
registers are implemented rather differently from those affecting lanes
in vector registers. Then, it's important that such insns be described
likewise differently in the scheduling m
On Mon, Sep 28, 2015 at 4:52 PM, Evandro Menezes wrote:
> In some micro-architectures the insns to load or store pairs of vector
> registers are implemented rather differently from those affecting lanes in
> vector registers. Then, it's important that such insns be described
> likewise differentl
