On Tue, Apr 3, 2018 at 12:48 AM, Jim Wilson wrote:
> On Fri, Mar 23, 2018 at 5:33 AM, Richard Biener
> wrote:
>> I'm leaving the "simple" combiner patch to review by others
>> but for RISC-V you could simply #define SHIFT_COUNT_TRUNCATED to zero
>> to fix the issue. Then add patterns if it turns
On Fri, Mar 23, 2018 at 5:33 AM, Richard Biener
wrote:
> I'm leaving the "simple" combiner patch to review by others
> but for RISC-V you could simply #define SHIFT_COUNT_TRUNCATED to zero
> to fix the issue. Then add patterns if it turns out to be required
> to avoid regressions. For example x8
On Thu, Mar 22, 2018 at 6:58 PM, Jim Wilson wrote:
> On Wed, Mar 21, 2018 at 2:45 AM, Richard Biener
> wrote:
>> On Tue, Mar 20, 2018 at 11:10 PM, Jim Wilson wrote:
>>> This fixes a wrong-code issue on RISC-V, but in theory could be a problem
>>> for
>>> any SHIFT_COUNT_TRUNCATED target.
>
>> I
On Wed, Mar 21, 2018 at 2:45 AM, Richard Biener
wrote:
> On Tue, Mar 20, 2018 at 11:10 PM, Jim Wilson wrote:
>> This fixes a wrong-code issue on RISC-V, but in theory could be a problem for
>> any SHIFT_COUNT_TRUNCATED target.
> IMHO the real issue is that SHIFT_COUNT_TRUNCATED is used for
> opt
On Tue, Mar 20, 2018 at 11:10 PM, Jim Wilson wrote:
> This fixes a wrong-code issue on RISC-V, but in theory could be a problem for
> any SHIFT_COUNT_TRUNCATED target.
>
> The testcase computes 46 or 47 (0x2e or 0x2f), then ANDs the value with 0xf,
> and then SHIFTs the value. On a SHIFT_COUNT_TR
