Hi,
On 1 November 2017 at 03:12, Jim Wilson wrote:
> On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote:
>> Ping ?
>>
>> I see that Jim has clarified the comments from Andrew.
>
> Andrew also suggested that we add a testcase to the testsuite. I
> didn't do that. I did put a testcas
Hi Jim,
On 1 November 2017 at 03:12, Jim Wilson wrote:
> On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote:
>> Ping ?
>>
>> I see that Jim has clarified the comments from Andrew.
>
> Andrew also suggested that we add a testcase to the testsuite. I
> didn't do that. I did put a tes
On Tue, 2017-10-31 at 14:35 +1100, Kugan Vivekanandarajah wrote:
> Ping ?
>
> I see that Jim has clarified the comments from Andrew.
Andrew also suggested that we add a testcase to the testsuite. I
didn't do that. I did put a testcase to reproduce in the bug report.
See
https://gcc.gnu.org
Ping ?
I see that Jim has clarified the comments from Andrew.
Thanks,
Kugan
On 13 October 2017 at 08:48, Jim Wilson wrote:
> On Fri, 2017-09-22 at 14:11 -0700, Andrew Pinski wrote:
>> On Fri, Sep 22, 2017 at 11:39 AM, Jim Wilson
>> wrote:
>> >
>> > On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pins
On Fri, 2017-09-22 at 14:11 -0700, Andrew Pinski wrote:
> On Fri, Sep 22, 2017 at 11:39 AM, Jim Wilson
> wrote:
> >
> > On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski
> > wrote:
> > >
> > > Two overall comments:
> > > * What about splitting register_offset into two different
> > > elements,
>
On Fri, Sep 22, 2017 at 11:39 AM, Jim Wilson wrote:
> On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski wrote:
>> Two overall comments:
>> * What about splitting register_offset into two different elements,
>> one for non 128bit modes and one for 128bit (and more; OI, etc.) modes
>> so you get bett
Hi Jim,
This looks like a general issue with reg+reg addressing modes being generated in
cases where it is not correct. I haven't looked at lmbench for a while, but it
generated
absolutely horrible code like:
add x1, x0, #120
ldr v0, [x2, x1]
add x1, x0, #128
ldr v1, [x2, x1]
If this is still h
On Fri, Sep 22, 2017 at 10:58 AM, Andrew Pinski wrote:
> Two overall comments:
> * What about splitting register_offset into two different elements,
> one for non 128bit modes and one for 128bit (and more; OI, etc.) modes
> so you get better address generation right away for the simd load
> cases
On Fri, Sep 22, 2017 at 8:59 AM, Jim Wilson wrote:
> On Fri, Sep 22, 2017 at 8:49 AM, Jim Wilson wrote:
>> On Falkor, because of an idiosyncracy of how the pipelines are designed, a
>> quad-word store using a reg+reg addressing mode is almost twice as slow as an
>> add followed by a quad-word sto
On Fri, Sep 22, 2017 at 8:49 AM, Jim Wilson wrote:
> On Falkor, because of an idiosyncracy of how the pipelines are designed, a
> quad-word store using a reg+reg addressing mode is almost twice as slow as an
> add followed by a quad-word store with a single reg addressing mode. So we
> get better
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