On Fri, Mar 1, 2024 at 4:07 AM Robin Dapp wrote:
>
> Hi Han,
>
> in addition to what Juzhe mentioned (and that late-combine is going
> to handle such cases) it should be noted that register pressure
> should not be the only consideration here. Many uarchs have a higher
> latency for register-file
Hi Han,
in addition to what Juzhe mentioned (and that late-combine is going
to handle such cases) it should be noted that register pressure
should not be the only consideration here. Many uarchs have a higher
latency for register-file-crossing moves. At least without spilling
the vv variant is p
Hi, han. My comment for this patch is same as
[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
-- Original --
From: "demin.han"
