Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Take a quick look and maybe fix it like that, but I am not sure the layout is what they want. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index eb665188caf..1692e43de10 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21714,7 +21714,7 @@ vector intrinsic specification, whi

Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

On 10/11/23 19:05, juzhe.zh...@rivai.ai wrote: Plz revert it. It blocks development of all targets. We have specific policies for reversion. In general we want to give folks time to fix the problem rather than reverting, resubmitting, etc. Mary, the issue is the doc changes are apparently

Re: Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Plz revert it. It blocks development of all targets. juzhe.zh...@rivai.ai From: Andrew Pinski Date: 2023-10-12 09:03 To: juzhe.zh...@rivai.ai CC: gcc-patches; jeffreyalaw; Kito.cheng; kito.cheng; Robin Dapp Subject: Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions On Wed, Oct 11, 2023

Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

On Wed, Oct 11, 2023 at 6:01 PM juzhe.zh...@rivai.ai wrote: > > ../../../../gcc/gcc/doc/extend.texi:21708: warning: node next `RISC-V Vector > Intrinsics' in menu `CORE-V Built-in Functions' and in sectioning `RX > Built-in Functions' differ > ../../../../gcc/gcc/doc/extend.texi:21716: warning:

RISC-V: Support CORE-V XCVMAC and XCVALU extensions

../../../../gcc/gcc/doc/extend.texi:21708: warning: node next `RISC-V Vector Intrinsics' in menu `CORE-V Built-in Functions' and in sectioning `RX Built-in Functions' differ ../../../../gcc/gcc/doc/extend.texi:21716: warning: node `RX Built-in Functions' is next for `CORE-V Built-in Functions' i

Re: [PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

On 10/11/23 06:06, Mary Bennett wrote: This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However,

[PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are inv

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Just repeat what I said on the mailing list again :P it's LGTM, just need to rebase to deal with riscv.opt related changes :) On Sat, Sep 30, 2023 at 8:02 PM Mary Bennett wrote: > > Thank you for reviewing this patch. > > v1->v2: > * Add XCValu RTL. > * Change assembly mnemonics from mixed c

[PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

Thank you for reviewing this patch. v1->v2: * Add XCValu RTL. * Change assembly mnemonics from mixed case to lower case. v2->v3: * Change commit message from past tense to present. * Add documentation for new dg-effective-targets. This patch series presents the comprehensive implementati

[PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are inv

[PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are inv