Tilman Sauerbeck [2013-02-24 17:00]:
> Richard Earnshaw [2013-02-20 11:00]:
> > On 19/02/13 22:26, Tilman Sauerbeck wrote:
> > >I don't get why relaxing the restrictions for the
> > >andsi3_compare0_scratch pattern results in a mismatch for the
> > >zeroextractsi_compare0_scratch one.
> > >
> > >An
Richard Earnshaw [2013-02-20 11:00]:
> On 19/02/13 22:26, Tilman Sauerbeck wrote:
> >I don't get why relaxing the restrictions for the
> >andsi3_compare0_scratch pattern results in a mismatch for the
> >zeroextractsi_compare0_scratch one.
> >
> >Any ideas?
>
> Because of the way combine works. It
On 19/02/13 22:26, Tilman Sauerbeck wrote:
I don't get why relaxing the restrictions for the
andsi3_compare0_scratch pattern results in a mismatch for the
zeroextractsi_compare0_scratch one.
Any ideas?
Because of the way combine works. It first tries to find a pattern that
doesn't have a clo
Tilman Sauerbeck [2013-02-19 23:26]:
> However it breaks the case where the 2nd operand is a const_int that
> *can* be used as an immediate (eg 0x80), and ends up generating the
> AND/CMP combination.
... and that would be because I changed the operand patterns in
zeroextractsi_compare0_scratch a
Richard Earnshaw [2013-02-19 15:12]:
Hi,
thanks for your reply.
> [...]
> However, the question you need to be asking is why the pattern immediately
> before the one you've added is not matching. The compiler knows how to add
> clobbers, so I'm surprised that you're finding a new pattern to be
>
On 18/02/13 21:47, Tilman Sauerbeck wrote:
Hi,
adding the instruction pattern below fixes my testcase for PR 56110;
however I'm not sure if adding a new pattern is the correct way to go.
I duplicated the andsi3_compare0_scratch pattern, and lifted the
requirement that the 2nd operand be an arm_n
Tilman Sauerbeck [2013-02-18 22:47]:
> [...]
> + "TARGET_32BIT"
> + "@
> + tst%?\\t%0, %1"
> [...]
I managed to post the wrong diff -- line 2 in the citation should be
omitted of course. Sorry.
Regards,
Tilman
--
A: Because it messes up the order in which people normally read text.
Q: Why
Hi,
adding the instruction pattern below fixes my testcase for PR 56110;
however I'm not sure if adding a new pattern is the correct way to go.
I duplicated the andsi3_compare0_scratch pattern, and lifted the
requirement that the 2nd operand be an arm_not_operand. I didn't copy
over the clobber pa
