Cc: Robin Dapp ; jeffreyalaw ;
Wang, Yanzhang ; kito.cheng
Subject: RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
By logically, Yes, we should not change that but here I would like to put all
enable related code together, will remove this part as it may has no
; jeffreyalaw ;
Wang, Yanzhang ; kito.cheng
Subject: Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
OK. But why change the place of these
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the exten
t;yes")
-
- (and (eq_attr "ext" "vector")
- (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-09 14:23
To: juzhe.zh..
gt;> thing is removed?
The same as above, move to the place after than type attr definition and only
add fp_vector_disable here.
>> This should be in vector.md instead of riscv.md
It will trigger "unknown attribute `fp_vector_disabled' in definition of
attribute `enabled'"
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
- (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
- (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
- (match_test "TARGET_HARD_FLOAT"))
- (const_st
