...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Wed, 19 Apr 2023, Li, Pan2 wrote:
> Hi Richard,
>
> Do you have any idea about this? I leverage git gcc-commit-mklog, it
> will generate something
ization.c
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 2:47 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
> richard.sandif...@arm.com; Wang, Yanzhang
> Subject: RE:
ches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the v
...@arm.com; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> we have below sample code.
&g
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> we have below sample code.
>
> vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl)
> {
> return __riscv_vmorn_mm_b32(v1, v1, vl);
> }
>
