RE: [PATCH v1] RISC-V: Bugfix for RVV integer reduction in ZVE32/64.

: Bugfix for RVV integer reduction in ZVE32/64. +/* Nonzero if MODE is a vector float mode. */ +#define VECTOR_FLOAT_MODE_P(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT) Why you add this? Remove it. Otherwise, LGTM. juzhe.zh...@rivai.ai

Re: [PATCH v1] RISC-V: Bugfix for RVV integer reduction in ZVE32/64.

+/* Nonzero if MODE is a vector float mode. */ +#define VECTOR_FLOAT_MODE_P(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT) Why you add this? Remove it. Otherwise, LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-06-16 15:28 To: gcc-patches CC: juzhe.zhong; rd