PING: [PATCH] x86: Add preserve_none and update no_caller_saved_registers attributes

2025-04-28 Thread H.J. Lu
On Fri, Apr 18, 2025 at 7:10 PM H.J. Lu wrote: > > Add preserve_none attribute which is similar to no_callee_saved_registers > attribute, except on x86-64, r12, r13, r14, r15, rdi and rsi registers are > used for integer parameter passing. This can be used in an interpreter > to avoid saving/rest

Re: PING: [PATCH] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-28 Thread H.J. Lu
On Tue, Apr 22, 2025 at 10:01 AM Hongtao Liu wrote: > > On Mon, Apr 21, 2025 at 4:30 PM H.J. Lu wrote: > > > > On Mon, Apr 21, 2025 at 11:29 AM Hongtao Liu wrote: > > > > > > On Sat, Apr 19, 2025 at 1:25 PM H.J. Lu wrote: > > > > > > > > On Sun, Dec 1, 2024 at 7:50 AM H.J. Lu wrote: > > > > >

Re: PING: [PATCH] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-21 Thread Hongtao Liu
On Mon, Apr 21, 2025 at 4:30 PM H.J. Lu wrote: > > On Mon, Apr 21, 2025 at 11:29 AM Hongtao Liu wrote: > > > > On Sat, Apr 19, 2025 at 1:25 PM H.J. Lu wrote: > > > > > > On Sun, Dec 1, 2024 at 7:50 AM H.J. Lu wrote: > > > > > > > > For all different modes of all 0s/1s vectors, we can use the si

Re: PING: [PATCH] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-21 Thread H.J. Lu
On Mon, Apr 21, 2025 at 11:29 AM Hongtao Liu wrote: > > On Sat, Apr 19, 2025 at 1:25 PM H.J. Lu wrote: > > > > On Sun, Dec 1, 2024 at 7:50 AM H.J. Lu wrote: > > > > > > For all different modes of all 0s/1s vectors, we can use the single widest > > > all 0s/1s vector register for all 0s/1s vector

Re: PING: [PATCH] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-20 Thread Hongtao Liu
On Sat, Apr 19, 2025 at 1:25 PM H.J. Lu wrote: > > On Sun, Dec 1, 2024 at 7:50 AM H.J. Lu wrote: > > > > For all different modes of all 0s/1s vectors, we can use the single widest > > all 0s/1s vector register for all 0s/1s vector uses in the whole function. > > Add a pass to generate a single wi

PING: [PATCH] x86: Add a pass to remove redundant all 0s/1s vector load

2025-04-18 Thread H.J. Lu
On Sun, Dec 1, 2024 at 7:50 AM H.J. Lu wrote: > > For all different modes of all 0s/1s vectors, we can use the single widest > all 0s/1s vector register for all 0s/1s vector uses in the whole function. > Add a pass to generate a single widest all 0s/1s vector set instruction at > entry of the near

Re: PING [PATCH] x86: Add ix86_ifunc_ref_local_ok

2022-07-31 Thread Uros Bizjak via Gcc-patches
On Wed, Jul 27, 2022 at 4:47 PM H.J. Lu wrote: > > On Thu, Jul 21, 2022 at 11:53 AM H.J. Lu wrote: > > > > We can't always use the PLT entry as the function address for local IFUNC > > functions. When the PIC register is needed for PLT call, indirect call > > via the PLT entry will fail since th

PING [PATCH] x86: Add ix86_ifunc_ref_local_ok

2022-07-27 Thread H.J. Lu via Gcc-patches
On Thu, Jul 21, 2022 at 11:53 AM H.J. Lu wrote: > > We can't always use the PLT entry as the function address for local IFUNC > functions. When the PIC register is needed for PLT call, indirect call > via the PLT entry will fail since the PIC register may not be set up > properly for indirect cal

PING: [PATCH] x86: Add

2020-10-02 Thread H.J. Lu via Gcc-patches
On Wed, Sep 23, 2020 at 10:58 AM H.J. Lu wrote: > > For sources which can't use any vector instructions, and > cannot be included for compiler intrinsics: > > $ echo "#include " | gcc -S -O2 -mno-sse -mno-mmx -x c - > In file included from /usr/include/stdlib.h:1013, > from > /

PING [PATCH] x86: Add cmpmemsi for -minline-all-stringops

2020-08-19 Thread H.J. Lu via Gcc-patches
On Tue, May 19, 2020 at 5:14 AM H.J. Lu wrote: > > On Tue, May 19, 2020 at 1:48 AM Uros Bizjak wrote: > > > > On Sun, May 17, 2020 at 7:06 PM H.J. Lu wrote: > > > > > > Duplicate the cmpstrn pattern for cmpmem. The only difference is that > > > the length argument of cmpmem is guaranteed to be

PING: [PATCH] x86: Add UNSPECV_PATCHABLE_AREA

2020-05-22 Thread H.J. Lu via Gcc-patches
On Sat, May 2, 2020 at 4:55 AM H.J. Lu wrote: > > Currently patchable area is at the wrong place. It is placed immediately > after function label, before both .cfi_startproc and ENDBR. This patch > adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and > changes ENDBR insertion pa

PING [PATCH] x86: Add -mzero-caller-saved-regs=[skip|used-gpr|all-gpr|used|all]

2018-11-29 Thread H.J. Lu
On Wed, Oct 31, 2018 at 12:42 PM H.J. Lu wrote: > > On Thu, Sep 27, 2018 at 7:58 AM Richard Biener > wrote: > > > > On Thu, Sep 27, 2018 at 3:16 PM H.J. Lu wrote: > > > > > > On Thu, Sep 27, 2018 at 6:08 AM, Szabolcs Nagy > > > wrote: > > > > On 26/09/18 19:10, H.J. Lu wrote: > > > >> > > > >>