Hi Jeff, Richard.
None of the RTL optimzers look at TRAP_IF w.r.t optimiizations.
I've decided to add some code to cprop.c and simplification primetives to
simply_rtx () this do work once
I fixed cprop to run on my testcase whicg only had functiions which 3 blocks
currently it think theses noth
On 07/10/2013 09:38 AM, Graham Stott wrote:
Hi Jeff, Richard,
Not sure if that working.
I created some rtl using TRAP_IF to represent the TEQ and emiited via an
expander
The TRAP_IF rtl make ait all the way though the rtl optimizers which are run
after expand
even though it should be possibl
Graham Stott writes:
> Not sure if that working.
>
> I created some rtl using TRAP_IF to represent the TEQ and emiited via an
> expander
>
> The TRAP_IF rtl make ait all the way though the rtl optimizers which are
> run after expand
> even though it should be possible to determine is false.
>
>
>
Hi Jeff, Richard,
Not sure if that working.
I created some rtl using TRAP_IF to represent the TEQ and emiited via an
expander
The TRAP_IF rtl make ait all the way though the rtl optimizers which are run
after expand
even though it should be possible to determine is false.
(insn 7 3 20 2 (se
On 07/09/2013 11:28 AM, Richard Sandiford wrote:
Graham Stott writes:
Hi Richard, Jeff.
Richard what's your idea for exposing things early enough so that VRP
can eliminate the need for a trao-if-zero insn iif possible.
Well, I was thinking of doing it in expand. I.e. get the MIPS div*, mod*
Graham Stott writes:
> Isn't that to late for VRP its run twice before expand pass.
Exactly why I said:
With Jeff's comment about VRP though, it sounds like he had different
ideas
:-) I suggested expand because I'd have expected the rtl optimisers to
deal with the cases your patterns were
Richard,
Isn't that to late for VRP its run twice before expand pass.
Graham
Graham Stott writes:
> Hi Richard, Jeff.
>
> Richard what's your idea for exposing things early enough so that VRP
> can eliminate the need for a trao-if-zero insn iif possible.
Well, I was thinking of doing it in expand. I.e. get the MIPS div*, mod*
and divmod* patterns to emit an explicit trap
Hi Richard, Jeff.
Richard what's your idea for exposing things early enough so that VRP can
eliminate the need for
a trao-if-zero insn iif possible.
Graham
On 07/04/2013 04:04 AM, Graham Stott wrote:
Hi Jeff, Richard
We could possibly also use VRP to change signed division to unsigned division
when dividing a
non-negative signed operand by a power of 2 because then the sign bit will be 0
and we could do
the division using logical shift right.
Se
Hi Jeff, Richard
We could possibly also use VRP to change signed division to unsigned division
when dividing a
non-negative signed operand by a power of 2 because then the sign bit will be 0
and we could do
the division using logical shift right.
Graham
On 07/03/13 11:42, Richard Sandiford wrote:
Graham Stott writes:
Hi Richard,
This patch attemps to elimate the TEQ instruction div DIV/MOD instructions
if possible (i.e the numerator is known to be non-zero)
I have introduced and seperated UNSPEC UNSPEC_SET_HILO_NOTRAP
which is generation by
Graham Stott writes:
> Hi Richard,
>
> This patch attemps to elimate the TEQ instruction div DIV/MOD instructions
> if possible (i.e the numerator is known to be non-zero)
>
> I have introduced and seperated UNSPEC UNSPEC_SET_HILO_NOTRAP
> which is generation by a peephole2 when the trap is kn
Hi Richard,
This patch attemps to elimate the TEQ instruction div DIV/MOD instructions
if possible (i.e the numerator is known to be non-zero)
I have introduced and seperated UNSPEC UNSPEC_SET_HILO_NOTRAP
which is generation by a peephole2 when the trap is known not to be required.
The peepho
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