On Tue, 10 May 2011, Bernd Schmidt wrote:
> On C6X, every jump instruction has 5 delay slots which can be filled
> with normally scheduled instructions. With an issue width of 8
> insns/cycle, this means that up to 40 insns can be issued after the jump
> insn before the jump's side-effect takes pla
On 05/11/2011 10:04 AM, Richard Sandiford wrote:
> Neat! It'll be interesting to see how easy it would be to convert
> recog and in-tree delayed-branch targets to use this form instead of
> SEQUENCEs. It'd certainly be a big step towards keeping the CFG
> around during and after md-reorg. I migh
Bernd Schmidt writes:
> Because of this problem, I've chosen a different model for this patch.
> Before calling the final sched_ebb pass, the port must split jump insns
> (or anything that should have delay slots) into two separate insns, a
> real insn and a shadow. As an example,
>
> (jump_insn
On C6X, every jump instruction has 5 delay slots which can be filled
with normally scheduled instructions. With an issue width of 8
insns/cycle, this means that up to 40 insns can be issued after the jump
insn before the jump's side-effect takes place. I didn't particularaly
feel like using reorg.c
