On Thu, May 16, 2013 at 12:05 PM, Marc Glisse wrote:
> On Thu, 16 May 2013, Richard Biener wrote:
>
>> On Thu, May 16, 2013 at 8:42 AM, Marc Glisse wrote:
>>>
>>> Hello,
>>>
>>> we can get into a cycle where:
>>> (x<0)|1 becomes (x<0)?-1:1
>>> and
>>> (y?-1:1) becomes y|1
>>>
>>> Contrary to what
On Thu, 16 May 2013, Richard Biener wrote:
On Thu, May 16, 2013 at 8:42 AM, Marc Glisse wrote:
Hello,
we can get into a cycle where:
(x<0)|1 becomes (x<0)?-1:1
and
(y?-1:1) becomes y|1
Contrary to what I posted in the PR, I am disabling the second
transformation here. It can be done later (t
On Thu, May 16, 2013 at 8:42 AM, Marc Glisse wrote:
> Hello,
>
> we can get into a cycle where:
> (x<0)|1 becomes (x<0)?-1:1
> and
> (y?-1:1) becomes y|1
>
> Contrary to what I posted in the PR, I am disabling the second
> transformation here. It can be done later (the x86 target partially does it
Hello,
we can get into a cycle where:
(x<0)|1 becomes (x<0)?-1:1
and
(y?-1:1) becomes y|1
Contrary to what I posted in the PR, I am disabling the second
transformation here. It can be done later (the x86 target partially does
it in the vcond expansion), and the VEC_COND_EXPR allows us to perfo
