t; From: Hongtao Liu
> > Sent: 01 July 2022 03:40
> > To: Roger Sayle
> > Cc: GCC Patches
> > Subject: Re: [x86 PATCH] UNSPEC_PALIGNR optimizations and clean-ups.
> >
> > On Fri, Jul 1, 2022 at 10:12 AM Hongtao Liu wrote:
> > >
> > > On Fri, Jul
.
Thanks in advance,
Roger
--
> -Original Message-
> From: Hongtao Liu
> Sent: 01 July 2022 03:40
> To: Roger Sayle
> Cc: GCC Patches
> Subject: Re: [x86 PATCH] UNSPEC_PALIGNR optimizations and clean-ups.
>
> On Fri, Jul 1, 2022 at 10:12 AM Hongtao Liu wrote:
> >
On Fri, Jul 1, 2022 at 10:12 AM Hongtao Liu wrote:
>
> On Fri, Jul 1, 2022 at 2:42 AM Roger Sayle wrote:
> >
> >
> > This patch is a follow-up to Hongtao's fix for PR target/105854. That
> > fix is perfectly correct, but the thing that caught my eye was why is
> > the compiler generating a shift
On Fri, Jul 1, 2022 at 2:42 AM Roger Sayle wrote:
>
>
> This patch is a follow-up to Hongtao's fix for PR target/105854. That
> fix is perfectly correct, but the thing that caught my eye was why is
> the compiler generating a shift by zero at all. Digging deeper it
> turns out that we can easily
This patch is a follow-up to Hongtao's fix for PR target/105854. That
fix is perfectly correct, but the thing that caught my eye was why is
the compiler generating a shift by zero at all. Digging deeper it
turns out that we can easily optimize __builtin_ia32_palignr for
alignments of 0 and 64 re
