On Tue, Jan 10, 2023 at 4:01 PM Roger Sayle wrote:
>
>
> Hi Richard and Uros,
> I believe I've managed to reduce a minimal test case that exhibits the
> underlying
> problem with reload. The following snippet when compiled on x86-64 with
> -O2:
>
> void ext(int x);
> void foo(int x, int y) { ext
ps.
Cheers,
Roger
--
> -Original Message-
> From: Richard Sandiford
> Sent: 10 January 2023 10:48
> To: Uros Bizjak
> Cc: GCC Patches ; Roger Sayle
>
> Subject: Re: [x86 PATCH] PR rtl-optimization/107991: peephole2 to tweak
> register allocation.
>
> Uros B
Uros Bizjak writes:
> On Mon, Jan 9, 2023 at 4:01 PM Roger Sayle wrote:
>>
>>
>> This patch addresses PR rtl-optimization/107991, which is a P2 regression
>> where GCC currently requires more "mov" instructions than GCC 7.
>>
>> The x86's two address ISA creates some interesting challenges for re
On Mon, Jan 9, 2023 at 4:01 PM Roger Sayle wrote:
>
>
> This patch addresses PR rtl-optimization/107991, which is a P2 regression
> where GCC currently requires more "mov" instructions than GCC 7.
>
> The x86's two address ISA creates some interesting challenges for reload.
> For example, the tric
This patch addresses PR rtl-optimization/107991, which is a P2 regression
where GCC currently requires more "mov" instructions than GCC 7.
The x86's two address ISA creates some interesting challenges for reload.
For example, the tricky "x = y - x" usually needs to be implemented on x86
as
