[to-be-committed] [RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern

So for this bug we have what appears to me to just be a bogus pattern. Essentially the pattern tries to detect cases where we have an SI mode value and we can use the Zbs instructions to manipulate a bit. Conceptually that's great. The problem is the pattern assumes that SI objects are sign

[to-be-committed][RISC-V][V2] Fix type on vector move patterns

Updated version of my prior patch to fix type attributes on the pre-allocation vector move pattern. This version just adds a suitable set of attributes to a second pattern that was obviously wrong. Passed on my tester for rv64 and rv32 crosses. Bootstrapped and regression tested on riscv64-l

[to-be-committed][RISC-V][V2]

This is primarily Sergei's work, my contributions were limited to merging his expander with the one that's on the trunk, allowing non-constant value and trivial testsuite adjustments due to option renaming. I'm doing setmem first because it's the easiest. The others will follow soon enough.