Re: [committed, amdgcn] Enable QI/HImode vector moves

2019-12-09 Thread Andrew Stubbs
Oops, please consider this patch as submitted from my @codesourcery.com address, for copyright assignment purposes. Andrew On 06/12/2019 17:31, Andrew Stubbs wrote: Hi all, This patch re-enables the V64QImode and V64HImode for GCN. GCC does not make these easy to work with because there is (

Re: [committed, amdgcn] Enable QI/HImode vector moves

2019-12-09 Thread Richard Sandiford
Andrew Stubbs writes: > On 06/12/2019 18:21, Richard Sandiford wrote: >> Andrew Stubbs writes: >>> Hi all, >>> >>> This patch re-enables the V64QImode and V64HImode for GCN. >>> >>> GCC does not make these easy to work with because there is (was?) an >>> assumption that vector registers do not ha

Re: [committed, amdgcn] Enable QI/HImode vector moves

2019-12-09 Thread Andrew Stubbs
On 06/12/2019 18:21, Richard Sandiford wrote: Andrew Stubbs writes: Hi all, This patch re-enables the V64QImode and V64HImode for GCN. GCC does not make these easy to work with because there is (was?) an assumption that vector registers do not have excess bits in vector registers, and therefo

Re: [committed, amdgcn] Enable QI/HImode vector moves

2019-12-06 Thread Richard Sandiford
Andrew Stubbs writes: > Hi all, > > This patch re-enables the V64QImode and V64HImode for GCN. > > GCC does not make these easy to work with because there is (was?) an > assumption that vector registers do not have excess bits in vector > registers, and therefore does not need to worry about tru

[committed, amdgcn] Enable QI/HImode vector moves

2019-12-06 Thread Andrew Stubbs
Hi all, This patch re-enables the V64QImode and V64HImode for GCN. GCC does not make these easy to work with because there is (was?) an assumption that vector registers do not have excess bits in vector registers, and therefore does not need to worry about truncating or extending smaller type