On Fri, Oct 28, 2016 at 07:27:56PM +0200, Eric Botcazou wrote:
> Thanks for the hint. The hook is the way to go I think because BITS_PER_WORD
> is not a constant, so the default would not be properly initialized. Here's
> a
> tentative patch, I'll add a couple of SPARC-specific testcases if ac
> Then to some extent defining WORD_REGISTER_OPERATIONS on SPARC is a lie,
> it only has "INT_REGISTER_OPERATIONS", i.e. all operations smaller than
> int are performed on the whole register, int operations can be really done
> in SImode in the IL (no need to sign/zero extend anything to DImode, if
On Fri, Oct 21, 2016 at 11:18:31AM +0200, Eric Botcazou wrote:
> /* For sub-word operations, if target doesn't have them, start
>with precres widening right away, otherwise do it only
>if the most simple cases can't be used. */
> if (WORD_REGISTER_OPERATIONS
> &
SPARC can expose the CC register before reload so the implementation is direct
as on x86 and ARM. Like ARM, there is no support for multiplication at all,
but support for 64-bit operations in 32-bit mode; the latter would give rise
to complex patterns for signed arithmetic involving TImode in 3
