Re: [RS6000] PR72802 part 2, reload ICE

2016-08-08 Thread Alan Modra
Also committed to gcc-6 branch. PR target/72802 * config/rs6000/rs6000.md (mov_hardfloat): Sort alternatives. Put loads first, then stores, and reg/reg moves within same class later. Delete attr length. testsuite/ * gcc.c-torture/compile/pr72802.c: New. d

Re: [RS6000] PR72802 part 2, reload ICE

2016-08-08 Thread Segher Boessenkool
On Mon, Aug 08, 2016 at 04:27:22PM +0930, Alan Modra wrote: > PR target/72802 > * config/rs6000/rs6000.md (mov_hardflow): Sort "hardfloat". > alternatives. Put loads first, then stores, and reg/reg moves > within same class later. Delete attr length. > testsuite/ >

Re: [RS6000] PR72802 part 2, reload ICE

2016-08-07 Thread Alan Modra
On Fri, Aug 05, 2016 at 08:31:45PM -0500, Segher Boessenkool wrote: > On Sat, Aug 06, 2016 at 10:53:33AM +0930, Alan Modra wrote: > > On Fri, Aug 05, 2016 at 06:01:47PM -0500, Segher Boessenkool wrote: > > > I agree reg-reg moves should come after reg-mem moves, but is it such > > > a good idea to

Re: [RS6000] PR72802 part 2, reload ICE

2016-08-05 Thread Segher Boessenkool
On Sat, Aug 06, 2016 at 10:53:33AM +0930, Alan Modra wrote: > On Fri, Aug 05, 2016 at 06:01:47PM -0500, Segher Boessenkool wrote: > > On Fri, Aug 05, 2016 at 02:20:40PM +0930, Alan Modra wrote: > > > Here are the reload costs for the various alternatives of > > > movsf_hardfloat: > > > "=!r, !r, m

Re: [RS6000] PR72802 part 2, reload ICE

2016-08-05 Thread Alan Modra
On Fri, Aug 05, 2016 at 06:01:47PM -0500, Segher Boessenkool wrote: > On Fri, Aug 05, 2016 at 02:20:40PM +0930, Alan Modra wrote: > > Here are the reload costs for the various alternatives of > > movsf_hardfloat: > > "=!r, !r, m, f, ww, ww, !r, f, wb, m, wY, wu, Z,?wn, ?r,*c*l, !r, *h" > > "

Re: [RS6000] PR72802 part 2, reload ICE

2016-08-05 Thread Segher Boessenkool
On Fri, Aug 05, 2016 at 02:20:40PM +0930, Alan Modra wrote: > Here are the reload costs for the various alternatives of > movsf_hardfloat: > "=!r, !r, m, f, ww, ww, !r, f, wb, m, wY, wu, Z,?wn, ?r,*c*l, !r, *h" > "r, m, r, f, ww, j, j, m, wY, f, wb, Z, wu, r, wn, r, *h, 0" > 617

[RS6000] PR72802 part 2, reload ICE

2016-08-04 Thread Alan Modra
After fixing the constraint problem, we hit an "insn does not satisfy its constraints" with -mno-lra on the following insn, a vector load from mem which has an invalid offset: (insn 631 630 1122 12 (set (reg:SF 108 31 [orig:260 pretmp_44 ] [260]) (mem:SF (plus:DI (reg:DI 30 30 [orig:338 ivt