On 5 May 2025 20:42:34 CEST, Jeff Law wrote:
diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c
b/gcc/testsuite/gcc.target/riscv/pr119971.c
new file mode 100644
index 000..c3f23b05ec3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr119971.c
@@ -0,0 +1,24 @@
+/* { dg-do compile
ommit 05d75c5bfcf923bc0258b79a08c5861590c5a2b9
Author: Jeff Law
Date: Mon May 5 17:14:29 2025 -0600
[RISC-V][PR target/119971] Avoid losing shift count masking
As is outlined in the PR, we have a few define_insn_and_split patterns which
optimize away explicit masking of shift/bit positions whe
As is outlined in the PR, we have a few define_insn_and_split patterns
which optimize away explicit masking of shift/bit positions when the
masking matches what the hardware's behavior.
A small number of those define_insn_and_split patterns generate a single
instruction. It's fairly elegant i
