Hi!
On Thu, Mar 10, 2022 at 09:54:55AM -0800, Patrick O'Neill wrote:
> I added this enforcement during the combine pass since it looks at the
> cost of certian expressions and can rely on the target to tell the
> pass that clobber-ops are cheaper than regular ops.
That is not a reason to put targ
Hi Patrick:
There is few direction in my mind:
1. Model the C extension right in riscv.md
2. Write peephole2 pattern.
3. Implement a RISC-V specific register renaming pass.
1. Model the C extension right in riscv.md
Currently we rely the GNU as to compress the instruction to C
extension, and ac
RISC-V's C-extension describes 2-byte instructions with special
constraints. One of those constraints is that one of the sources/dest
registers are equal (op will clobber one of it's operands). This patch
adds support for combining simple sequences:
r1 = r2 + r3 (4 bytes)
r2 DEAD
r4 = r1 + r5 (4
