Re: [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez

2023-04-21 Thread Jeff Law via Gcc-patches
On 2/10/23 15:41, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combina

[RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez

2023-02-10 Thread Philipp Tomsich
Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combination of XVentanaCondOps and Zbs are available, th