On 2023/08/29 6:12, Jeff Law wrote:
>
>
> On 8/9/23 00:11, Tsukasa OI via Gcc-patches wrote:
>> From: Tsukasa OI
>>
>> The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
>> (in the assembler). However, GCC emits "pause" unconditionally, making
>> an assembler error whil
On 8/9/23 00:11, Tsukasa OI via Gcc-patches wrote:
From: Tsukasa OI
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler). However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zi
From: Tsukasa OI
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler). However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' extension disabled.
However, the "pause" in