On Fri, 24 Mar 2017, Jakub Jelinek wrote:
> On Mon, Mar 06, 2017 at 12:53:38PM +0100, Richard Biener wrote:
> > I think these are all bugs and should be fixed and thus this checking
> > is good.
> >
> > Of course we'd better not break (too many) targets at this point...
>
> I've tested it today
On Mon, Mar 06, 2017 at 12:53:38PM +0100, Richard Biener wrote:
> I think these are all bugs and should be fixed and thus this checking
> is good.
>
> Of course we'd better not break (too many) targets at this point...
I've tested it today and it passed on all targets I've tried make s-recog
on,
On 08/03/17 15:51, Bill Schmidt wrote:
On Mar 6, 2017, at 6:55 AM, Jakub Jelinek wrote:
Nice. So just arm, aarch64 and rs6000 to go.
Proposed patch for rs6000 is here:
https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00372.html.
arm patch is here https://gcc.gnu.org/ml/gcc-patches/2017-03/m
> On Mar 6, 2017, at 6:55 AM, Jakub Jelinek wrote:
>
> Nice. So just arm, aarch64 and rs6000 to go.
Proposed patch for rs6000 is here:
https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00372.html.
Thanks,
Bill
On Mon, Mar 06, 2017 at 12:27:31PM +, Matthew Fortune wrote:
> Jakub Jelinek writes:
> > >
> > > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > > elements, expected 4
> > > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > > elements, expected 4
Jakub Jelinek writes:
> >
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > elements, expected 4
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > elements, expected 4
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> >
On Mon, Mar 6, 2017 at 11:48 AM, Jakub Jelinek wrote:
> Hi!
>
> CCing also arm, aarch64 and mips maintainers on the issues in their
> backends. It is likely if such VEC_SELECTs are visible to simplify-rtx.c,
> it would ICE on them.
Kyrill, could you take a look at ARM and AArch64 ? I'm still in
Hi Jakub,
On 06/03/17 11:48, Jakub Jelinek wrote:
Hi!
CCing also arm, aarch64 and mips maintainers on the issues in their
backends. It is likely if such VEC_SELECTs are visible to simplify-rtx.c,
it would ICE on them.
On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
../../gcc/c
On Fri, 3 Mar 2017, Jakub Jelinek wrote:
> Hi!
>
> When working on PR79812 which was caused by bugs in x86 define_insn
> (used vec_select with parallel as last operand with incorrect number of
> operands), I wrote following sanity checking.
>
> The thing is that e.g. simplify-rtx.c already has s
Hi!
CCing also arm, aarch64 and mips maintainers on the issues in their
backends. It is likely if such VEC_SELECTs are visible to simplify-rtx.c,
it would ICE on them.
On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
> ../../gcc/config/aarch64/aarch64-simd.md:79:1: DImode of first
On Fri, Mar 03, 2017 at 02:58:06PM -0600, Segher Boessenkool wrote:
> On Fri, Mar 03, 2017 at 03:43:03PM -0500, Michael Meissner wrote:
> > On Fri, Mar 03, 2017 at 02:19:57PM -0600, Segher Boessenkool wrote:
> > > On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
> > > Yeah, it looks l
On Fri, Mar 03, 2017 at 03:43:03PM -0500, Michael Meissner wrote:
> On Fri, Mar 03, 2017 at 02:19:57PM -0600, Segher Boessenkool wrote:
> > On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
> > Yeah, it looks like these patterns should use VSX_D instead of VSX_LE.
> > Mike, you know th
On Fri, Mar 03, 2017 at 02:19:57PM -0600, Segher Boessenkool wrote:
> Hi,
>
> On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
> > E.g. in vsx.md the thing is that
> > the pattern uses an iterator with 2 V2?? modes in it and then V1TI mode,
> > and uses exactly two elements in parall
Hi,
On Fri, Mar 03, 2017 at 05:28:27PM +0100, Jakub Jelinek wrote:
> E.g. in vsx.md the thing is that
> the pattern uses an iterator with 2 V2?? modes in it and then V1TI mode,
> and uses exactly two elements in paralle, which doesn't make any sense
> for V1TI.
>
> ../../gcc/config/rs6000/vsx.md:
Hi!
When working on PR79812 which was caused by bugs in x86 define_insn
(used vec_select with parallel as last operand with incorrect number of
operands), I wrote following sanity checking.
The thing is that e.g. simplify-rtx.c already has such assertions:
if (!VECTOR_MODE_P (mode))
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