Re: [RFC] RISCV: Combine Pass Clobber Ops

On Thu, Mar 10, 2022 at 9:36 AM Patrick O'Neill wrote: > > RISC-V's C-extension describes 2-byte instructions with special > constraints. One of those constraints is that one of the sources/dest > registers are equal (op will clobber one of it's operands). This patch > adds support for combining s

[RFC] RISCV: Combine Pass Clobber Ops

RISC-V's C-extension describes 2-byte instructions with special constraints. One of those constraints is that one of the sources/dest registers are equal (op will clobber one of it's operands). This patch adds support for combining simple sequences: r1 = r2 + r3 (4 bytes) r2 DEAD r4 = r1 + r5 (4