Hi Kyrill,
On 2019/8/28 16:57, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 8/28/19 9:47 AM, Shaokun Zhang wrote:
>> Hi Kyrill,
>>
>> On 2019/8/27 18:16, Kyrill Tkachov wrote:
>>> Hi Shaokun,
>>>
>>> On 8/22/19 3:10 PM, Shaokun Zhang wrote:
The DCache clean & ICache invalidation requirements f
Hi Shaokun,
On 8/28/19 9:47 AM, Shaokun Zhang wrote:
Hi Kyrill,
On 2019/8/27 18:16, Kyrill Tkachov wrote:
Hi Shaokun,
On 8/22/19 3:10 PM, Shaokun Zhang wrote:
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_
Hi Kyrill,
On 2019/8/27 18:16, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 8/22/19 3:10 PM, Shaokun Zhang wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable through new fields in CTR_EL0.
>> Let's support the two bits if they are
Hi Shaokun,
On 8/22/19 3:10 PM, Shaokun Zhang wrote:
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
Let's support the two bits if they are enabled, then we can get some
performance benefit from this featur
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
Let's support the two bits if they are enabled, then we can get some
performance benefit from this feature.
2019-08-22 Shaokun Zhang
* config/aarch64/sy
