Re: [RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-16 Thread Maciej W. Rozycki
On Sat, 14 May 2022, Palmer Dabbelt wrote: > > Hmm, should we? We only support `-misa-spec=<2.2|20190608|20191213>' > > already and this update is fine for r.2.2+. If someone has pre-r.2.2 hw, > > then it's been already unsupported even before this change (as from GCC 11 > > AFAICS). Have I mi

Re: [RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-14 Thread Palmer Dabbelt
On Fri, 13 May 2022 12:57:35 PDT (-0700), ma...@embecosm.com wrote: On Fri, 13 May 2022, Palmer Dabbelt wrote: Yep. We should have a NEWS entry, though, as this one is user-visible and may be tricky to sort out if it turns out there is some HW lurking around that has the old behavior. Hmm,

Re: [RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-13 Thread Maciej W. Rozycki
On Fri, 13 May 2022, Palmer Dabbelt wrote: > Yep. We should have a NEWS entry, though, as this one is user-visible and may > be tricky to sort out if it turns out there is some HW lurking around that has > the old behavior. Hmm, should we? We only support `-misa-spec=<2.2|20190608|20191213>'

Re: [RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-13 Thread Palmer Dabbelt
On Tue, 10 May 2022 08:48:33 PDT (-0700), gcc-patches@gcc.gnu.org wrote: Thanks Maciej! Yep. We should have a NEWS entry, though, as this one is user-visible and may be tricky to sort out if it turns out there is some HW lurking around that has the old behavior. On Tue, May 10, 2022 at 10

Re: [RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-10 Thread Kito Cheng via Gcc-patches
Thanks Maciej! On Tue, May 10, 2022 at 10:05 PM Maciej W. Rozycki wrote: > > As at r2.2 of the RISC-V ISA specification[1] (equivalent to version 2.0 > of the "F" and "D" standard architecture extensions for single-precision > and double-precision floating-point respectively) the FMIN and FMAX >

[RESEND][committed v4] RISC-V: Provide `fmin'/`fmax' RTL patterns

2022-05-10 Thread Maciej W. Rozycki
As at r2.2 of the RISC-V ISA specification[1] (equivalent to version 2.0 of the "F" and "D" standard architecture extensions for single-precision and double-precision floating-point respectively) the FMIN and FMAX machine instructions fully match our requirement for the `fminM3' and `fmaxM3' st