On 26 January 2016 at 16:04, James Greenhalgh wrote:
> 2016-01-25 James Greenhalgh
>
> * config/aarch64/aarch64.md
> (arch64_sqrdmlh_lane): Fix register
> constraints for operand 3.
> (aarch64_sqrdmlh_laneq): Likewise.
>
OK /Marcus
On Mon, Feb 08, 2016 at 12:52:00PM +, James Greenhalgh wrote:
> On Tue, Jan 26, 2016 at 04:04:47PM +, James Greenhalgh wrote:
> >
> > Hi,
> >
> > In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> > available when compiling with -march=armv8.1-a are only usable wit
On Tue, Jan 26, 2016 at 04:04:47PM +, James Greenhalgh wrote:
>
> Hi,
>
> In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
> available when compiling with -march=armv8.1-a are only usable with
> a register number in the range 0 to 15 for operand 3, as gas will point
>
On 01/26/16 10:04, James Greenhalgh wrote:
Hi,
In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
available when compiling with -march=armv8.1-a are only usable with
a register number in the range 0 to 15 for operand 3, as gas will point
out:
Error: register number out
Hi,
In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
available when compiling with -march=armv8.1-a are only usable with
a register number in the range 0 to 15 for operand 3, as gas will point
out:
Error: register number out of range 0 to 15 at
operand 3 -- `sqrdmls
