On Tue, 2018-09-04 at 17:20 +, Wilco Dijkstra wrote:
> External Email
>
> Hi Steve,
>
> The latest version compiles the examples I used correctly, so it looks fine
> from that perspective (but see comments below). However the key point of
> the ABI is to enable better code generation when cal
Hi Steve,
The latest version compiles the examples I used correctly, so it looks fine
from that perspective (but see comments below). However the key point of
the ABI is to enable better code generation when calling a vector function,
and that will likely require further changes that may conflict
Hi Steve,
On 20/08/18 18:37, Steve Ellcey wrote:
On Tue, 2018-08-07 at 12:15 -0500, Segher Boessenkool wrote:
> > +/* { dg-final { scan-assembler-not "\[ \t\]stp\tq\[01234567\]" } }
> > */
> That's [0-7] but maybe you find [01234567] more readable here.
Segher, I fixed all the issues you poin
Ping. Any feedback from the Aarch64 maintainers?
Steve Ellcey
sell...@cavium.com
On Mon, 2018-08-20 at 10:37 -0700, Steve Ellcey wrote:
> On Tue, 2018-08-07 at 12:15 -0500, Segher Boessenkool wrote:
>
> >
> > >
> > > +/* { dg-final { scan-assembler-not "\[ \t\]stp\tq\[01234567\]" }
> > >
On Tue, 2018-08-07 at 12:15 -0500, Segher Boessenkool wrote:
> > +/* { dg-final { scan-assembler-not "\[ \t\]stp\tq\[01234567\]" } }
> > */
> That's [0-7] but maybe you find [01234567] more readable here.
Segher, I fixed all the issues you pointed out except this one. Since
there are some uses
Hi!
Some very trivial comments...
On Mon, Aug 06, 2018 at 03:13:52PM -0700, Steve Ellcey wrote:
> (aarch64_components_for_bb): Check for simd function.
> (aarch64_epilogue_uses): New function.
> (aarch64_process_components): Ditto.
> (aarch64_expand_prologue): Ditto.
>
I have a question about my own patch. In doing testing I realized
that if I use the aarch64_vector_pcs attribute on a platform without
SIMD (i.e. -march=armv8.1-a+nosimd) I get an ICE. That is obviously
not what we want but I was wondering what the right behaviour is.
We certainly don't want to
Thanks for the feedback Kyrill. I have updated my patch and attached
the new version to this email. The one change I did not make was to
remove load_pair_dw_tftf and store_pair_dw_tftf and use the
load_pair and vec_store_pair
patterns. Having to add two new iterators to remove two instructions
d
Hi Steve,
On 31/07/18 23:24, Steve Ellcey wrote:
Here is a new version of my patch to support the Aarch64 SIMD ABI [1]
in GCC. I think this is complete enought to be considered for check
in. I wrote a few new tests and put them in a new gcc.target/torture
directory so they would be run with mu
Here is a new version of my patch to support the Aarch64 SIMD ABI [1]
in GCC. I think this is complete enought to be considered for check
in. I wrote a few new tests and put them in a new gcc.target/torture
directory so they would be run with multiple optimization options. I
also verified that t
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