On Thu, Feb 01, 2018 at 02:43:17PM +, Renlin Li wrote:
> Hi James,
>
> Thanks for the review! I committed it on trunk.
>
> Is it Okay to backport this patch to release branch 5, 6,7?
> It applies cleanly without any logic changes.
6 and 7 yes, OK.
5 is no longer supported so may be a waste
Hi James,
Thanks for the review! I committed it on trunk.
Is it Okay to backport this patch to release branch 5, 6,7?
It applies cleanly without any logic changes.
Regards,
Renlin
On 31/01/18 17:56, James Greenhalgh wrote:
On Tue, Jan 30, 2018 at 03:45:17PM +, Renlin Li wrote:
Hi Richard
On Tue, Jan 30, 2018 at 03:45:17PM +, Renlin Li wrote:
> Hi Richard,
>
> Thanks for the review!
>
> On 29/01/18 20:23, Richard Sandiford wrote:
> >
> > The patch looks good to me FWIW. How about adding something like
> > the following testcase?
> >
> >
Hi Richard,
Thanks for the review!
On 29/01/18 20:23, Richard Sandiford wrote:
The patch looks good to me FWIW. How about adding something like
the following testcase?
/* { dg-do run } */
/* { dg-options "-O2" } */
typedef void (*fun) (void);
void __att
Renlin Li writes:
> Hi all,
>
> In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
> temporary register.
>
> When the compiler is performing sibcall optimization. It has the chance to use
> ip0/ip1 register for indirect function call to hold the address. However,
> thos
Ping ~
On 11/12/17 15:27, Renlin Li wrote:
Hi all,
In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
temporary register.
When the compiler is performing sibcall optimization. It has the chance to use
ip0/ip1 register for indirect function call to hold the address. H
Hi all,
In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
temporary register.
When the compiler is performing sibcall optimization. It has the chance to use
ip0/ip1 register for indirect function call to hold the address. However, those
two register might
be clobbere
