uot; " svu, 0")))]
What is "svu" ?
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-22 08:59
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v6 2/3] RISC-V: Add crypto machine descriptions
Patch v6: Swap the operator order of v
Patch v6: Swap the operator order of vandn.vv.Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v5: Add vec_duplicate operator.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vecto
