Discussed in the patchworks meeting with Jeff Law and decided to move
forward with the trailing fence compatibility approach. If the trailing
fence becomes a performance issue and people want to generate A.6 code,
we'll need a PSABI change to identify which mapping a binary uses. We'll
cross that
On 4/28/23 15:42, Hans Boehm wrote:
The concern with making the new behavior non-default is of course that
the generated code will eventually end up on an A.7-capable platform.
Yea, certainly a significant concern in general, though probably not for
Ventana. I expect we'll have folks rebuild
The RISC-V psABI pull request is at
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378 . Pointers to
Paul Kirth's corresponding LLVM patches are also there.
On Fri, Apr 28, 2023 at 2:42 PM Hans Boehm wrote:
> The concern with making the new behavior non-default is of course that the
>
The concern with making the new behavior non-default is of course that the
generated code will eventually end up on an A.7-capable platform.
An A.6-classic option for compiling code that will never run on a newer
machine seems OK. But I'm not sure that seq_cst stores are dynamically
frequent enoug
On Fri, 28 Apr 2023 10:40:15 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'N
On 4/27/23 10:22, Patrick O'Neill wrote:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
Should be "PR target/89835"
gcc/ChangeLog:
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR 89835
gcc/ChangeLog:
* config/riscv/sync.md:
gcc/testsuite/ChangeLog:
* gcc.tar
