, Yanzhang
Subject: RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Thanks Juzhe for reviewing. I see, this way may have even smaller code change
which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.
Pan
From: juzhe.zh...@rivai.ai
; Li,
Pan2 ; Wang, Yanzhang
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
In this patch, you add TARGET_ZVFH into VF iterator which is not correct.
When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.
For vfadd, it is true we should enable "vfadd" for T
& riscv_vector::float_mode_supported_p (mode)"
"vf.vv\t%0,%3,%4%p1"
[(set_attr "type" "")
(set_attr "mode" "")])
bool
float_mode_supported_p (machine_mode mode)
{
if (GET_MODE_INNER (mode) == HFmode)
return TARGET_ZVFH;
ret
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the
From: Pan Li
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: P
