oshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Yes.
juzhe.zh...@rivai.ai
发件人： joshua
发送时
uot;gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Does theadvector has extension instructions ?
Show me the
送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
(vec_duplicate:RVVM1QI (reg:QI 147
Find the RTL define pseudo 147 to me.
I guess
：2024年1月11日(星期四) 20:13
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specif
ches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patter
17:57
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
"cooper.joshua";
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
24年1月11日(星期四) 17:32
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsi
mbly stage.
--
发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月11日(星期四) 17:28
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add
[(unspec:
+ [(match_operand: 0 "vector_mask_operand" "vmWc1")
+ (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 5 "const_int_operand" " i")
+ (reg:SI VL_REGNUM)
+
送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
You mean which pattern optimized sext/vzext pattern?
I didn't see the
elated to vwmul.
--
发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月11日(星期四) 17:17
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[P
ew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
sext/zext will be generated in O2 even without corresponding intrinsics.
-
ew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
"cooper.joshua";
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
enum required_ext
{
VECTOR_EXT, /* Vector extension */
+ XTHEADVECTOR_EXT, /* XTheadVect
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
quot;
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
So vlb has not only sew = 8 ?
But why do you add intrinsics as follow
： joshua
发送时间： 2024-01-10 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The key difference between vlb/vlh/vlw is not
quot;
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The key difference between vlb/vlh/vlw is not output type too.
Their dif
...@rivai.ai
发送时间：2024年1月10日(星期三) 19:00
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvect
：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
"cooper.joshua";
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
i8_v
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* con
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* con
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