Re: [PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-10-19 Thread chenglulu
在 2023/8/20 下午4:25, Xi Ruoyao 写道: On Thu, 2023-08-17 at 15:20 +0800, Chenghui Pan wrote: Seems ARMv8-A only guarantees to preserve low 64-bit value of NEON/floating-point register value. I'm not sure that I modify the testcase in the right way and maybe we need more investigations. Any ideas o

Re: [PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-08-20 Thread Xi Ruoyao via Gcc-patches
On Thu, 2023-08-17 at 15:20 +0800, Chenghui Pan wrote: > Seems ARMv8-A only guarantees to preserve low 64-bit value of > NEON/floating-point register value. I'm not sure that I modify the > testcase in the right way and maybe we need more investigations. Any > ideas or suggestion? Sorry, the follo

Re: [PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-08-17 Thread Chenghui Pan
Hi! I try to investigate on this problem, and modify the testcase to compile and run on aarch64 for reference, but I get some strange result (comment shows the info that I see by stepping through by using gdb): typedef double __attribute__((vector_size(16))) v2df; void use1(double d) {} __attrib

Re: [PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-08-15 Thread Xi Ruoyao via Gcc-patches
The implementation fails to handle this test case properly: typedef double __attribute__((vector_size(32))) v4df; void use1(double); __attribute__((noipa)) double use(double) { register double x asm("f24") = 114.514; __asm__("" : "+f" (x)); return x; } void test(void) {

[PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target.

2023-08-14 Thread Chenghui Pan
This is an update of: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626194.html This version of patch set only introduces some small simplications of implementation. Because I missed the size limitation of mail size, the huge testsuite patches of v2 and v3 are not shown in the mail list. S