[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

There are some xtheadvector instructions that differ from RVV1.0 apart from simply adding "th." prefix. For example, RVV1.0 load/store instructions will have SEW while xtheadvector not; RVV1.0 will have "o" for indexed-ordered store instructions while xtheadvecotr not; xtheadvector and RVV1.0 have

Re: [PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

Please move those code logic to thead.cc, e.g. if (TARGET_XTHEADVECTOR) return th_asm_output_opcode (asm_out_file, p); And then implement th_asm_output_opcode in thead.cc. On Wed, Jan 3, 2024 at 10:39 AM Jun Sha (Joshua) wrote: > > There are some xtheadvector instructions that differ from RV

[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

There are some xtheadvector instructions that differ from RVV1.0 apart from simply adding "th." prefix. For example, RVV1.0 load/store instructions will have SEW while xtheadvector not; RVV1.0 will have "o" for indexed-ordered store instructions while xtheadvecotr not; xtheadvector and RVV1.0 have