andn")
+ (set_attr "mode" "")])
EEW = 64 in RV32 system handling is missing ?
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-13 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan; Feng Wang
Subject: [PATCH v3 3/4] RISC-V: Add cryp
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destination register.
This patch add the crypto machine descriptions(vector-crypto.md) and
some new iterators which are used by crypto vector ext.
Co-Authored by: Songhe Zhu
Co-Authored b
